Integrated circuit packages are often formed in a layered fashion, where layers of dielectric material are overlaid with a metallic material that is patterned to fabricate power, ground, and trace connections to connect an integrated circuit to a printed circuit board. Various components are formed in the metal pattern in close proximity within the integrated circuit package, which in some configurations results in unwanted electrical interaction among the components. Various mechanisms are formed in the metal pattern to mitigate the unwanted electrical interaction. At times some combinations of components and mechanisms result in a mechanical weakness of the integrated circuit package.
The description above is presented as a general overview of related art in this field and should not be construed as an admission that any of the information it contains constitutes prior art against the present patent application.